| A 0.3 pJ/bit 20 Gb/s/wire parallel interface for die-to-die communication B Dehlaghi, AC Carusone IEEE Journal of Solid-State Circuits 51 (11), 2690-2701, 2016 | 54 | 2016 |
| 30.5 A 1.41 pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS S Shahramian, B Dehlaghi, J Liang, R Bespalko, D Dunwell, J Bailey, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 482-484, 2019 | 33 | 2019 |
| Highly-linear time-difference amplifier with low sensitivity to process variations B Dehlaghi, S Magierowski, L Belostotski Electronics letters 47 (13), 743-745, 2011 | 31 | 2011 |
| Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in s S Shahramian, B Dehlaghi, AC Carusone IEEE Journal of Solid-State Circuits 51 (12), 3192-3203, 2016 | 28 | 2016 |
| A systematic methodology to design analog predistortion linearizer for dual inflection power amplifiers S Rezaei, MS Hashmi, B Dehlaghi, FM Ghannouchi 2011 IEEE MTT-S International Microwave Symposium, 1-4, 2011 | 23 | 2011 |
| A 1.41-pJ/b 56-Gb/s PAM-4 receiver using enhanced transition utilization CDR and genetic adaptation algorithms in 7-nm CMOS B Dehlaghi, S Shahramian, J Liang, R Bespalko, D Dunwell, J Bailey, ... IEEE Solid-State Circuits Letters 2 (11), 248-251, 2019 | 16 | 2019 |
| Ultra-short-reach interconnects for die-to-die links: Global bandwidth demands in microcosm B Dehlaghi, N Wary, TC Carusone IEEE Solid-State Circuits Magazine 11 (2), 42-53, 2019 | 16 | 2019 |
| A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS B Dehlaghi, AC Carusone 2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015 | 15 | 2015 |
| A 12.5-Gb/s on-chip oscilloscope to measure eye diagrams and jitter histograms of high-speed signals B Dehlaghi, S Magierowski, L Belostotski IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (5 …, 2013 | 15 | 2013 |
| 23.7 A 16Gb/s 1 IIR+ 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs S Shahramian, B Dehlaghi, AC Carusone 2016 IEEE International Solid-State Circuits Conference (ISSCC), 410-411, 2016 | 12 | 2016 |
| Ultra-short-reach interconnects for package-level integration AC Carusone, B Dehlaghi, R Beerkens, D Tonietto 2016 IEEE Optical Interconnects Conference (OI), 10-11, 2016 | 8 | 2016 |
| Interconnect technologies for terabit-per-second die-to-die interfaces B Dehlaghi, R Beerkens, D Tonietto, AC Carusone 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 1-4, 2016 | 5 | 2016 |
| Signal generation apparatus and method, and system L Gao, B Dehlaghi US Patent 11,165,609, 2021 | 3 | 2021 |
| Receiver recovering a signal clock from a received data signal, and a clock recovery method implemented in the receiver B Dehlaghi, S Shahramian US Patent 10,135,604, 2018 | 3 | 2018 |
| Decision feedback equalizers and methods of decision feedback equalization S Shahramian, B Dehlaghi US Patent 10,187,234, 2019 | 2 | 2019 |
| Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation YF Zhang, J Liang, S Shahramian, B Dehlaghi, R Bespalko, M O’Farrel, ... IEEE Solid-State Circuits Letters 3, 25-28, 2019 | 1 | 2019 |
| System and method for recovering a clock signal E Chong, MS Jalali, B Dehlaghi US Patent 11,675,386, 2023 | | 2023 |
| 2019 Index IEEE Solid-State Circuits Magazine Vol. 11 E Afshari, M Alioto, A Altvater, M Aseeri, R Baker, D Bankman, M Brox, ... IEEE Solid-State Circuits Magazine 11 (4), 1, 2019 | | 2019 |
| Termination for single-ended receiver E Chong, S Shahramian, B Dehlaghi, AC Carusone US Patent 10,033,419, 2018 | | 2018 |
