| A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices O Petura, U Mureddu, N Bochard, V Fischer, L Bossuet Field Programmable Logic and Applications (FPL), 2016 26th International …, 2016 | 106 | 2016 |
| Design and testing methodologies for true random number generators towards industry certification J Balasch, F Bernard, V Fischer, M Grujić, M Laban, O Petura, V Rožić, ... 2018 IEEE 23rd European Test Symposium (ETS), 1-10, 2018 | 27 | 2018 |
| Evaluation and monitoring of free running oscillators serving as source of randomness EN Allini, M Skórski, O Petura, F Bernard, M Laban, V Fischer IACR Transactions on Cryptographic Hardware and Embedded Systems I 2018, 214 …, 2018 | 17 | 2018 |
| Optimization of the PLL configuration in a PLL-based TRNG design EN Allini, O Petura, V Fischer, F Bernard Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018 …, 2018 | 16 | 2018 |
| True random number generators for cryptography: Design, securing and evaluation O Petura Université de Lyon, 2019 | 14 | 2019 |
| Optimization of the PLL based TRNG design using the genetic algorithm O Petura, U Mureddu, N Bochard, V Fischer Circuits and Systems (ISCAS), 2017 IEEE International Symposium on, 1-4, 2017 | 13 | 2017 |
| Evariste III: A new multi-FPGA system for fair benchmarking of hardware dependent cryptographic primitives N Bochard, C Marchand, O Peťura, L Bossuet, V Fischer Workshop on Cryptographic Hardware and Embedded Systems, CHES 2015, 2015 | 9 | 2015 |
| Complete activation scheme for FPGA-oriented IP cores design protection B Colombier, U Mureddu, M Laban, O Petura, L Bossuet, V Fischer Field Programmable Logic and Applications (FPL), 2017 27th International …, 2017 | 3 | 2017 |
| Efficient design of Oscillator based Physical Unclonable Functions on Flash FPGAs U Mureddu, O Petura, N Bochard, L Bossuet, V Fischer Verification and Security Workshop (IVSW), 2017 IEEE 2nd International, 146-151, 2017 | 2 | 2017 |
| EMBEDDED SENSOR NODE FOR UWB RADAR NETWORK BASED SHORT-RANGE TRACKING OF MOVING PERSONS M Drutarovsky, D Kocur, O Petura, J Fortes, S Slovak, M Laban, P Galajda, ... ДВНЗ" Ужгородський національний університет", 2016 | 2 | 2016 |
| Evaluation of AIS-20/31 compliant TRNG cores implemented on FPGAs O Petura, U Mureddu, N Bochard, V Fischer, L Bossuet 6th Conference on Trustworthy Manufacturing and Utilization of Secure …, 2016 | 1 | 2016 |
| Two Methods of the Clock Jitter Measurement Aimed at Embedded TRNG Testing O Petura, M Laban, EN Allini, V Fischer Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2018), 2018 | | 2018 |
| Complete activation scheme for IP design protection B Colombier, U Mureddu, M Laban, O Petura, L Bossuet, V Fischer IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2017 | | 2017 |
Lilian BossuetProfessor, University Jean Monnet, Saint-Etienne - Laboratoire Hubert Curien - CNRSVerified email at univ-st-etienne.fr
