| Approximate buffers for reducing memory requirements: Case study on SKA H Miomandre, JF Nezan, D Menard, A Campbell, A Griffin, S Hall, A Ensor 2020 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2020 | 2* | 2020 |
| Demonstrating the spider runtime for reconfigurable dataflow graphs execution onto a dma-based manycore processor H Miomandre, J Hascoët, K Desnos, K Martin, BD De Dinechin, JF Nezan IEEE International Workshop on Signal Processing Systems, 2017 | 2 | 2017 |
| Embedded runtime for reconfigurable dataflow graphs on manycore architectures H Miomandre, J Hascoët, K Desnos, KJM Martin, BD de Dinechin Kalray, ... Proceedings of the 9th Workshop and 7th Workshop on Parallel Programming and …, 2018 | 1 | 2018 |
| Automated Buffer Sizing of Dataflow Applications in a High-Level Synthesis Workflow A Honorat, M Dardaillon, H Miomandre, JF Nezan ACM Transactions on Reconfigurable Technology and Systems 17 (1), 1-26, 2024 | | 2024 |
| An Initial Framework for Prototyping the Radio-Inteferometric Imaging Pipeline S Wang, N Gac, H Miomandre, JF Nezan, K Desnos, F Orieux DASIP 2024-Workshop on Design and Architectures for Signal and Image Processing, 2024 | | 2024 |
| Approximated Computing-based Methods for Hardware Resources Reduction Targeting Heterogeneous Systems H Miomandre INSA de Rennes, 2022 | | 2022 |
| Design Space Exploration for Memory-Oriented Approximate Computing Techniques H Miomandre, JF Nezan, D Ménard 2022 IEEE 33rd International Conference on Application-specific Systems …, 2022 | | 2022 |
| Influence of Dataflow Graph Moldable Parameters on Optimization Criteria A Honorat, T Bourgoin, H Miomandre, K Desnos, D Menard, JF Nezan International Workshop on Design and Architecture for Signal and Image …, 2022 | | 2022 |
| Site web IETR Equipe Video Analysis and Architecture Design for Embedded Resources (VAADER) A Honorat, T Bourgoin, H Miomandre, K Desnos, D Menard | | |
