| A signal correlation guided ATPG solver and its applications for solving difficult industrial cases F Lu, LC Wang, KT Cheng, J Moondanos, Z Hanna Proceedings of the 40th annual Design Automation Conference, 436-441, 2003 | 61 | 2003 |
| Sequential redundancy identification using verification techniques J Moondanos, J Abraham Proceedings International Test Conference 1992, 197-197, 1992 | 35 | 1992 |
| CLEVER: Divide and conquer combinational logic equivalence verification with false negative elimination J Moondanos, CH Seger, Z Hanna, D Kaiss International Conference on Computer Aided Verification, 131-143, 2001 | 32 | 2001 |
| An efficient diagnostic test pattern generation framework using boolean satisfiability F Zheng, KT Cheng, X Yan, J Moondanos, Z Hanna 16th Asian Test Symposium (ATS 2007), 288-294, 2007 | 30 | 2007 |
| Automatic verification of implementations of large circuits against HDL specifications YV Hoskote, JA Abraham, DS Fussell, J Moondanos IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1997 | 28 | 1997 |
| Method and system for formal verification of a circuit model using binary decision diagrams J Moondanos, CJ Seger, Z Hanna, DA Kaiss US Patent 6,564,358, 2003 | 25 | 2003 |
| An enhanced cut-points algorithm in formal equivalence verification Z Khasidashvili, J Moondanos, D Kaiss, Z Hanna Sixth IEEE International High-Level Design Validation and Test Workshop, 171-176, 2001 | 18 | 2001 |
| Jpeg encoding on the intel mxp5800: A platform-based design case study A Davare, Q Zhu, J Moondanos, A Sangiovanni-Vincentelli 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005., 89-94, 2005 | 17 | 2005 |
| A Signal Correlation Guided Circuit-SAT Solver. F Lu, LC Wang, Kwang-Ting (Tim) Cheng, J Moondanos, Z Hanna J. UCS 10 (12), 1629-1654, 2004 | 15 | 2004 |
| Generation of shorter sequences for high resolution error diagnosis using sequential sat SJ Pan, KT Cheng, J Moondanos, Z Hanna Asia and South Pacific Conference on Design Automation, 2006., 5 pp., 2006 | 13 | 2006 |
| TRANS: Efficient sequential verification of loop-free circuits Z Khasidashvili, J Moondanos, Z Hanna Seventh IEEE International High-Level Design Validation and Test Workshop …, 2002 | 9 | 2002 |
| Loop-Free Circuits Z Khasidashvili, J Moondanos, Z Hanna IEEE International High-Level Design Validation and Test Workshop 7, 115, 2002 | 9 | 2002 |
| Verification of circuits described in VHDL through extraction of design intent YV Hoskote, J Moondanos, JA Abraham, DS Fussell Proceedings of 7th International Conference on VLSI Design, 417-420, 1994 | 9 | 1994 |
| Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis N Evmorfopoulos, MA Rammou, G Stamoulis, J Moondanos 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 824-830, 2010 | 8 | 2010 |
| Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification J Moondanos, Z Khasidashvili, ZE Hanna US Patent 6,792,581, 2004 | 8 | 2004 |
| SystemC tutorial J Moondanos UC Berkeley EE249 Lecture Notes, 0 | 8 | |
| VERTEX: VERification of Transistor-level circuits based on model EXtraction J Moondanos, JA Wehbeh, JA Abrahamn, DG Saab 1993 European Conference on Design Automation with the European Event in …, 1993 | 7 | 1993 |
| Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification J Moondanos, Z Khasidashvili, ZE Hanna US Patent 7,159,201, 2007 | 6 | 2007 |
| Application of the retimed normal form to the formal equivalence verification of abstract RTL descriptions for pipelined designs Z Khasidashvili, J Moondanos, Z Hanna US Patent 7,117,465, 2006 | 6 | 2006 |
| Preserving synchronizing sequences of sequential circuits after retiming MN Mneimneh, KA Sakallah, J Moondanos ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE …, 2004 | 5 | 2004 |
