| Electromagnetic transient faults injection on a hardware and a software implementations of AES A Dehbaoui, JM Dutertre, B Robisson, A Tria 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 7-15, 2012 | 303 | 2012 |
| When clocks fail: On critical paths and clock faults M Agoyan, JM Dutertre, D Naccache, B Robisson, A Tria International conference on smart card research and advanced applications …, 2010 | 258 | 2010 |
| Fault model analysis of laser-induced faults in sram memory cells C Roscian, A Sarafianos, JM Dutertre, A Tria 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography, 89-98, 2013 | 131 | 2013 |
| How to flip a bit? M Agoyan, JM Dutertre, AP Mirbaha, D Naccache, AL Ribotta, A Tria 2010 IEEE 16th International On-Line Testing Symposium, 235-239, 2010 | 129 | 2010 |
| Efficiency of a glitch detector against electromagnetic fault injection L Zussa, A Dehbaoui, K Tobich, JM Dutertre, P Maurine, ... 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 107 | 2014 |
| Injection of transient faults using electromagnetic pulses-Practical results on a cryptographic system-. A Dehbaoui, JM Dutertre, B Robisson, P Orsatelli, P Maurine, A Tria IACR Cryptology EPrint Archive 2012, 123, 2012 | 93 | 2012 |
| Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism L Zussa, JM Dutertre, J Clediere, A Tria 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 110-115, 2013 | 91 | 2013 |
| Frontside laser fault injection on cryptosystems-Application to the AES'last round C Roscian, JM Dutertre, A Tria 2013 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2013 | 88 | 2013 |
| A side-channel and fault-attack resistant AES circuit working on duplicated complemented values M Doulcier-Verdier, JM Dutertre, J Fournier, JB Rigaud, B Robisson, ... 2011 IEEE International Solid-State Circuits Conference, 274-276, 2011 | 78 | 2011 |
| Laser-induced single-bit faults in flash memory: Instructions corruption on a 32-bit microcontroller B Colombier, A Menu, JM Dutertre, PA Moëllic, JB Rigaud, JL Danger 2019 IEEE International Symposium on Hardware Oriented Security and Trust …, 2019 | 72 | 2019 |
| Investigation of timing constraints violation as a fault injection means L Zussa, JM Dutertre, J Clédiere, B Robisson, A Tria 27th Conference on Design of Circuits and Integrated Systems (DCIS), Avignon …, 2012 | 71 | 2012 |
| Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model JM Dutertre, V Beroulle, P Candelier, S De Castro, LB Faber, ML Flottes, ... 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 1-6, 2018 | 62 | 2018 |
| Evidence of a larger EM-induced fault model S Ordas, L Guillaume-Sage, K Tobich, JM Dutertre, P Maurine Smart Card Research and Advanced Applications: 13th International Conference …, 2015 | 61 | 2015 |
| A DFA on AES based on the entropy of error distributions R Lashermes, G Reymond, JM Dutertre, J Fournier, B Robisson, A Tria 2012 workshop on fault diagnosis and tolerance in cryptography, 34-43, 2012 | 59 | 2012 |
| High-speed ring oscillator based sensors for remote side-channel attacks on FPGAs J Gravellier, JM Dutertre, Y Teglia, P Loubet-Moundi 2019 International conference on ReConFigurable computing and FPGAs …, 2019 | 56 | 2019 |
| Electromagnetic glitch on the AES round counter A Dehbaoui, AP Mirbaha, N Moro, JM Dutertre, A Tria International Workshop on Constructive Side-Channel Analysis and Secure …, 2013 | 54 | 2013 |
| Remote side-channel attacks on heterogeneous SoC J Gravellier, JM Dutertre, Y Teglia, PL Moundi, F Olivier Smart Card Research and Advanced Applications: 18th International Conference …, 2020 | 53 | 2020 |
| Single-bit DFA using multiple-byte laser fault injection M Agoyan, JM Dutertre, AP Mirbaha, D Naccache, AL Ribotta, A Tria 2010 IEEE International Conference on Technologies for Homeland Security …, 2010 | 49 | 2010 |
| Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter L Zussa, JM Dutertre, J Clediere, B Robisson 2014 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2014 | 44 | 2014 |
| Building the electrical model of the pulsed photoelectric laser stimulation of an NMOS transistor in 90nm technology A Sarafianos, O Gagliano, V Serradeil, M Lisart, JM Dutertre, A Tria 2013 IEEE International Reliability Physics Symposium (IRPS), 5B. 5.1-5B. 5.9, 2013 | 42 | 2013 |
Jean-Baptiste RigaudMines Saint-Etienne, CEA-Tech, Centre CMP, Departement SAS, F - 13541 Gardanne FranceVerified email at mines-stetienne.fr
