| Redefine: Runtime reconfigurable polymorphic asic M Alle, K Varadarajan, A Fell, N Joseph, S Das, P Biswas, J Chetia, A Rao, ... ACM Transactions on Embedded Computing Systems (TECS) 9 (2), 1-48, 2009 | 64 | 2009 |
| Force-directed scheduling for data flow graph mapping on coarse-grained reconfigurable architectures A Fell, ZE Rákossy, A Chattopadhyay 2014 International Conference on ReConFigurable Computing and FPGAs …, 2014 | 28 | 2014 |
| Compiling techniques for coarse grained runtime reconfigurable architectures M Alle, K Varadarajan, A Fell, SK Nandy, R Narayan Reconfigurable Computing: Architectures, Tools and Applications: 5th …, 2009 | 25 | 2009 |
| RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router J Nimmy, CR Reddy, K Varadarajan, M Alle, A Fell, SK Nandy, R Narayan 2008 International Conference on Application-Specific Systems, Architectures …, 2008 | 24 | 2008 |
| Synthesis of application accelerators on runtime reconfigurable hardware M Alle, K Varadarajan, RC Ramesh, J Nimmy, A Fell, A Rao, SK Nandy, ... 2008 International Conference on Application-Specific Systems, Architectures …, 2008 | 21 | 2008 |
| Generic routing rules and a scalable access enhancement for the network-on-chip reconnect A Fell, P Biswas, J Chetia, SK Nandy, R Narayan 2009 IEEE International SOC Conference (SOCC), 251-254, 2009 | 18 | 2009 |
| Symmetric -Means for Deep Neural Network Compression and Hardware Acceleration on FPGAs A Jain, P Goel, S Aggarwal, A Fell, S Anand IEEE Journal of Selected Topics in Signal Processing 14 (4), 737-749, 2020 | 17 | 2020 |
| TAD: Time side-channel attack defense of obfuscated source code A Fell, HT Pham, SK Lam Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | 14 | 2019 |
| Streaming FFT on REDEFINE-v2: An application-architecture design space exploration A Fell, M Alle, K Varadarajan, P Biswas, S Das, J Chetia, SK Nandy, ... Proceedings of the 2009 international conference on Compilers, architecture …, 2009 | 13 | 2009 |
| DFGenTool: A dataflow graph generation tool for coarse grain reconfigurable architectures M Mukherjee, A Fell, A Guha 2017 30th International Conference on VLSI Design and 2017 16th …, 2017 | 11 | 2017 |
| RRC, N M Alle, K Varadarajan, A Fell Joseph, S. Das, P. Biswas, J. Chetia, A. Rao, SK Nandy, and R. Narayan …, 2009 | 10 | 2009 |
| Method and System on Chip (SoC) for Adapting a Reconfigurable Hardware for an Application at Runtime SK Nandy, R Narayan, M Alle, K Vardarajan, A Fell, A Rao, R Reddy, ... US Patent App. 13/002,329, 2011 | 9 | 2011 |
| Method and System on Chip (SoC) for Adapting a Reconfigurable Hardware for an Application at Runtime SK Nandy, R Narayan, M Alle, K Vardarajan, A Fell, A Rao, R Reddy, ... US Patent App. 13/002,329, 2011 | 9 | 2011 |
| Method and System on Chip (SoC) for Adapting a Reconfigurable Hardware for an Application at Runtime SK Nandy, R Narayan, M Alle, K Vardarajan, A Fell, A Rao, R Reddy, ... US Patent App. 13/002,329, 2011 | 9 | 2011 |
| The marenostrum experimental exascale platform (MEEP) A Fell, DJ Mazure, TC Garcia, B Perez, X Teruel, P Wilson, JD Davis Supercomputing Frontiers and Innovations 8 (1), 62-81, 2021 | 8 | 2021 |
| Ramesh Reddy C., Nimmy Joseph, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsh Rao, SK Nandy, and Ranjani Narayan. REDEFINE: Runtime reconfigurable polymorphic ASIC M Alle, K Varadarajan, A Fell ACM Trans. Embed. Comput. Syst 9 (2), 1-48, 2009 | 7 | 2009 |
| Method and system on chip (SoC) for adapting a runtime reconfigurable hardware to decode a video stream SK Nandy, R Narayan, M Alle, K Vardarajan, A Fell, A Rao, R Reddy, ... US Patent 8,891,614, 2014 | 6 | 2014 |
| Method and system on chip (SoC) for adapting a runtime reconfigurable hardware to decode a video stream SK Nandy, R Narayan, M Alle, K Vardarajan, A Fell, A Rao, R Reddy, ... US Patent 8,891,614, 2014 | 6 | 2014 |
| Coyote: an open source simulation tool to enable RISC-V in HPC B Perez, A Fell, JD Davis 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 130-135, 2021 | 5 | 2021 |
| A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI R Kaur, A Fell, H Rawat 2015 28th IEEE International System-on-Chip Conference (SOCC), 310-315, 2015 | 5 | 2015 |
