A sharable built-in self-repair for semiconductor memories with 2-D redundancy scheme S Bahl 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI …, 2007 | 33 | 2007 |
On-chip and at-speed tester for testing and characterization of different types of memories S Bahl, B Singh US Patent 7,353,442, 2008 | 27 | 2008 |
Self programmable shared bist for testing multiple memories S Bahl US Patent 7,814,385, 2010 | 20 | 2010 |
Integrated circuit with reduced power consumption in a test mode, and related methods S Bahl, S Khullar US Patent 8,917,123, 2014 | 15 | 2014 |
Testing of multi-clock domains S Bahl, A Garg US Patent 8,381,051, 2013 | 15 | 2013 |
State of the art low capture power methodology S Bahl, R Mattiuzzo, S Khullar, A Garg, S Graniello, KS Abdel-Hafez, ... 2011 IEEE International Test Conference, 1-10, 2011 | 15 | 2011 |
Synchronous on-chip clock controllers S Bahl, S Khullar US Patent 9,264,049, 2016 | 14 | 2016 |
Unifying scan compression S Bahl, S Rungta, S Khullar, R Kapur, A Chandra, S Talluto, P Notiyath, ... 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2014 | 10 | 2014 |
Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing S Khullar, S Bahl US Patent 8,775,857, 2014 | 10 | 2014 |
Self-Programmable shared BIST for testing multiple memories S Bahl, V Srivastava 2008 13th European Test Symposium, 91-96, 2008 | 8 | 2008 |
Power aware shift and capture ATPG methodology for low power designs S Khullar, S Bahl 2011 Asian Test Symposium, 500-505, 2011 | 4 | 2011 |
Incremental small delay defect methodology P Cavenaghi, R Mattiuzzo, S Bahl, A Garg Proc. IEEE design automation conf (DAC’10), 2010 | 4 | 2010 |
A novel method for silicon configurable test flow and algorithms for testing different types of embedded memories through a shared controller S Bahl, B Singh IEEE Memory Technology, Design and Test, MTDT'04, 2004 | 4 | 2004 |
Monitoring on-chip clock control during integrated circuit testing S Khullar, S Bahl US Patent 9,234,938, 2016 | 3 | 2016 |
Testing of multi-clock domains S Bahl, A Garg US Patent 8,527,824, 2013 | 3 | 2013 |
EDA solutions to new-defect detection in advanced process technologies EJ Marinissen, G Vandling, SK Goel, F Hapke, J Rivers, N Mittermaier, ... 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 123-128, 2012 | 3 | 2012 |
Configurable length first-in first-out memory S Bahl, B Singh US Patent 7,321,520, 2008 | 3 | 2008 |
A novel method for silicon configurable test flow and algorithms for testing, debugging and characterizing different types of embedded memories through a shared controller S Bahl, B Singh Records of the 2004 International Workshop on Memory Technology, Design and …, 2004 | 3 | 2004 |
Method and apparatus for testing of a memory with redundancy elements T Roy, H Rawat, S Bahl, A Chhabra, N Jain, J Fultaria US Patent 8,458,545, 2013 | 2 | 2013 |
On-chip storage memory for storing variable data bits S Bahl, B Singh US Patent 7,372,755, 2008 | 2 | 2008 |