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Marius Minea
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State space reduction using partial order techniques
EM Clarke, O Grumberg, M Minea, D Peled
International Journal on Software Tools for Technology Transfer 2, 279-287, 1999
2751999
Static partial order reduction
R Kurshan, V Levin, M Minea, D Peled, H Yenigün
International Conference on Tools and Algorithms for the Construction and …, 1998
1501998
The AVANTSSAR platform for the automated validation of trust and security of service-oriented architectures
A Armando, W Arsac, T Avanesov, M Barletta, A Calvi, A Cappai, ...
Tools and Algorithms for the Construction and Analysis of Systems: 18th …, 2012
1412012
Assume-guarantee reasoning for hierarchical hybrid systems
TA Henzinger, M Minea, V Prabhu
Hybrid Systems: Computation and Control: 4th International Workshop, HSCC …, 2001
1212001
Computing quantitative characteristics of finite-state real-time systems
Campos, Marrero, Minea, Hiraishi
1994 Proceedings Real-Time Systems Symposium, 266-270, 1994
1201994
Relooper: refactoring for loop parallelism in Java
D Dig, M Tarce, C Radoi, M Minea, R Johnson
Proceedings of the 24th ACM SIGPLAN conference companion on Object oriented …, 2009
882009
Verus: a tool for quantitative analysis of finite-state real-time systems
S Campos, E Clarke, W Marrero, M Minea
Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers …, 1995
861995
Partial order reduction for model checking of timed automata
M Minea
International Conference on Concurrency Theory, 431-446, 1999
801999
Verifying the performance of the PCI local bus using symbolic techniques
S Campos, E Clarke, W Marrero, M Minea
Proceedings of ICCD'95 International Conference on Computer Design. VLSI in …, 1995
791995
Duplicate code detection using anti-unification
P Bulychev, M Minea
Proceedings of the spring/summer young researchers’ colloquium on software …, 2008
742008
Synthesis of VHDL concurrent processes
P Eles, M Minea, K Kuchcinski, Z Peng
EURO-DAC 94, 540-545, 1994
491994
The Verus tool: A quantitative approach to the formal verification of real-time systems
S Campos, E Clarke, M Minea
Computer Aided Verification: 9th International Conference, CAV'97 Haifa …, 1997
471997
An evaluation of duplicate code detection using anti-unification
P Bulychev, M Minea
Proc. 3rd International Workshop on Software Clones, 54-55, 2009
462009
Combining software and hardware verification techniques
RP Kurshan, V Levin, M Minea, D Peled, H Yenigün
Formal Methods in System Design 21, 251-280, 2002
432002
Compiling VHDL into a high-level synthesis design representation.
P Eles, K Kuchcinski, Z Peng, M Minea
EURO-DAC 92, 604-609, 1992
421992
Partial order reduction for verification of timed systems
M Minea
Carnegie Mellon University, 1999
391999
Timing analysis of industrial real-time systems
S Campos, E Clarke, W Marrero, M Minea
Proceedings of 1995 IEEE Workshop on Industrial-Strength Formal …, 1995
391995
Specifying and verifying partial order properties using template MSCs
B Genest, M Minea, A Muscholl, D Peled
International Conference on Foundations of Software Science and Computation …, 2004
332004
Equivalence checking using abstract BDDs
S Jha, Y Lu, M Minea, EM Clarke
Proceedings International Conference on Computer Design VLSI in Computers …, 1997
331997
Verifying hardware in its software context and vice-versa
RP Kurshan, V Levin, M Minea, DA Peled, H Yenigun
US Patent 6,209,120, 2001
312001
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