Raśl Silvera
Raśl Silvera
Waymo LLC
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Cited by
Evaluation of Blue Gene/Q hardware support for transactional memories
A Wang, M Gaudet, P Wu, JN Amaral, M Ohmacht, C Barton, R Silvera, ...
Proceedings of the 21st international conference on Parallel architectures …, 2012
Speculative thread execution with hardware transactional memory
ME Giampapa, TM Gooding, RE Silvera, KTA Wang, P Wu, X Zhuang
US Patent 8,438,568, 2013
Is the Schedule Clause Really Necessary in OpenMP?
E Ayguadé, B Blainey, A Duran, J Labarta, F Martinez, X Martorell, ...
International workshop on OpenMP applications and tools, 147-159, 2003
Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions
CM Barton, HW Cain III, BG Frey, HQ Le, MM Michael, RE Silvera, ...
US Patent App. 13/176,833, 2013
Mpads: memory-pooling-assisted data splitting
S Curial, P Zhao, JN Amaral, Y Gao, S Cui, R Silvera, R Archambault
Proceedings of the 7th international symposium on Memory management, 101-110, 2008
Forma A framework for safe automatic array reshaping
P Zhao, S Cui, Y Gao, R Silvera, JN Amaral
ACM Transactions on Programming Languages and Systems (TOPLAS) 30 (1), 2-es, 2007
Compiling source code
RG Archambault, S Cui, Y Gao, RE Silvera
US Patent 8,161,464, 2012
Mechanism to restrict parallelization of loops
RE Silvera, P Unnikrishnan, G Zhang
US Patent 8,104,030, 2012
setjmp/longjmp for speculative execution frameworks
RE Silvera, KTA Wang, P Wu, MW Yamashita, X Zhuang
US Patent 8,640,113, 2014
Hardware assist thread for increasing code parallelism
RP Hall, HQ Le, RE Silvera, B Sinharoy
US Patent 8,423,750, 2013
Method of SIMD-ization through data reshaping, padding, and alignment
RG Archambault, S Cui, Y Gao, RE Silvera
US Patent 7,856,627, 2010
A practical approach to DOACROSS parallelization
P Unnikrishnan, J Shirako, K Barton, S Chatterjee, R Silvera, V Sarkar
Euro-Par 2012 Parallel Processing: 18th International Conference, Euro-Par …, 2012
Lock caching for compound atomic operations on shared memory
RE Silvera, RJ Blainey
US Patent 7,228,391, 2007
Method and apparatus for improving data cache performance using inter-procedural strength reduction of global objects
RG Archambault, S Cui, Y Gao, RE Silvera
US Patent 7,555,748, 2009
Distributed counter and centralized sensor in barrier wait synchronization
RE Silvera, KA Stoodley, G Zhang
US Patent 7,487,501, 2009
Code motion based on live ranges in an optimizing compiler
S Cui, RE Silvera
US Patent 8,484,630, 2013
Simple Profile Rectifications Go a Long Way: Statistically Exploring and Alleviating the Effects of Sampling Errors for Program Optimizations
B Wu, M Zhou, X Shen, Y Gao, R Silvera, G Yiu
ECOOP 2013–Object-Oriented Programming: 27th European Conference …, 2013
OpenMP tasks in IBM XL compilers
X Teruel, P Unnikrishnan, X Martorell, E Ayguadé, R Silvera, G Zhang, ...
Proceedings of the 2008 conference of the center for advanced studies on …, 2008
Pipelined parallelization of multi-dimensional loops with multiple data dependencies
RE Silvera, P Unnikrishnan
US Patent 8,146,071, 2012
Method for simplifying compiler-generated software code
HH Li, RE Silvera
US Patent 7,856,628, 2010
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