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| Anton 2: raising the bar for performance and programmability in a special-purpose molecular dynamics supercomputer DE Shaw, JP Grossman, JA Bank, B Batson, JA Butts, JC Chao, ... SC'14: Proceedings of the International Conference for High Performance …, 2014 | 698 | 2014 |
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| Architecture validation for processors RC Ho, CH Yang, MA Horowitz, DL Dill Proceedings of the 22nd Annual International Symposium on Computer …, 1995 | 238 | 1995 |
| Chip placement with deep reinforcement learning A Mirhoseini, A Goldie, M Yazgan, J Jiang, E Songhori, S Wang, YJ Lee, ... arXiv preprint arXiv:2004.10746, 2020 | 224 | 2020 |
| Method for automatically generating checkers for finding functional defects in a description of a circuit TA Ly, JC Giomi, KC Mulam, PA Wilcox, DL Dill, IIP Estrada, CMR Ho, ... US Patent 6,175,946, 2001 | 99 | 2001 |
| Validation coverage analysis for complex digital designs RC Ho, MA Horowitz Proceedings of International Conference on Computer Aided Design, 146-151, 1996 | 91 | 1996 |
| Method for automatically searching for functional defects in a description of a circuit CMR Ho, RK Mardjuki, DL Dill, JC Lin, PF Yeung, PII Estrada, JC Giomi, ... US Patent 6,292,765, 2001 | 47 | 2001 |
| Measure of analysis performed in property checking JR Levitt, C Gauthron, CMR Ho, PF Yeung, KC Mulam, R Sathianathan US Patent 6,848,088, 2005 | 45 | 2005 |
| Method for automatically generating checkers for finding functional defects in a description of a circuit TA Ly, JC Giomi, KC Mulam, PA Wilcox, DL Dill, IIP Estrada, CMR Ho, ... US Patent 6,609,229, 2003 | 45 | 2003 |
| Selection of initial states for formal verification JAG Seawright, R Sathianathan, CG Gauthron, JR Levitt, KC Mulam, ... US Patent 7,454,324, 2008 | 43 | 2008 |
| Azade Nazi, Jiwoo Pak, Andy Tong, Kavya Srinivasa, William Hang, Emre Tuncer, Quoc V. Le, James Laudon, Richard Ho, Roger Carpenter, and Jeff Dean. 2021. A graph placement … A Mirhoseini, A Goldie, M Yazgan, JW Jiang, E Songhori, S Wang, YJ Lee, ... Nature 594 (7862), 01, 2021 | 38 | 2021 |
| Warehouse-scale video acceleration: co-design and deployment in the wild P Ranganathan, D Stodolsky, J Calow, J Dorfman, M Guevara, ... Proceedings of the 26th ACM International Conference on Architectural …, 2021 | 36 | 2021 |
| Post-silicon debug using formal verification waypoints CR Ho, M Theobald, B Batson, J Grossman, SC Wang, J Gagliardo, ... Design and Verification Conf, 2009 | 28 | 2009 |
| Validation tools for complex digital designs CMR Ho Stanford University, 1997 | 28 | 1997 |
| Method for automatically searching for functional defects in a description of a circuit CMR Ho, RK Mardjuki, DL Dill, JC Lin, PF Yeung, PI Estrada, JC Giomi, ... US Patent 6,885,983, 2005 | 27 | 2005 |
| Learning semantic representations to verify hardware designs S Vasudevan, WJ Jiang, D Bieber, R Singh, CR Ho, C Sutton Advances in Neural Information Processing Systems 34, 23491-23504, 2021 | 25 | 2021 |
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