| An evaluation of high-level mechanistic core models TE Carlson, W Heirman, S Eyerman, I Hur, L Eeckhout ACM Transactions on Architecture and Code Optimization (TACO) 11 (3), 1-25, 2014 | 395 | 2014 |
| A comprehensive approach to DRAM power management I Hur, C Lin 2008 IEEE 14th International Symposium on High Performance Computer …, 2008 | 187 | 2008 |
| Adaptive history-based memory schedulers I Hur, C Lin 37th International Symposium on Microarchitecture (MICRO-37'04), 343-354, 2004 | 183 | 2004 |
| Memory prefetching using adaptive stream detection I Hur, C Lin Microarchitecture, 2006. MICRO-39. 39th Annual IEEE/ACM International …, 2006 | 156 | 2006 |
| Power-aware multi-core simulation for early design stage hardware/software co-optimization W Heirman, S Sarkar, TE Carlson, I Hur, L Eeckhout Proceedings of the 21st international conference on Parallel architectures …, 2012 | 55 | 2012 |
| DRAM power management in a memory controller I Hur, C Lin US Patent 7,739,461, 2010 | 51 | 2010 |
| Discovering and understanding performance bottlenecks in transactional applications F Zyulkyarov, S Stipic, T Harris, OS Unsal, A Cristal, I Hur, M Valero Proceedings of the 19th international conference on Parallel architectures …, 2010 | 46 | 2010 |
| RMS-TM: A comprehensive benchmark suite for transactional memory systems G Kestor, V Karakostas, OS Unsal, A Cristal, I Hur, M Valero Proceeding of the second joint WOSP/SIPEW international conference on …, 2011 | 40 | 2011 |
| Near-side prefetch throttling: Adaptive prefetching for high-performance many-core processors W Heirman, KD Bois, Y Vandriessche, S Eyerman, I Hur Proceedings of the 27th International Conference on Parallel Architectures …, 2018 | 39 | 2018 |
| Undersubscribed threading on clustered cache architectures W Heirman, TE Carlson, K Van Craeynest, I Hur, A Jaleel, L Eeckhout 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 38 | 2014 |
| Memory scheduling for modern microprocessors I Hur, C Lin ACM Transactions on Computer Systems (TOCS) 25 (4), 10-es, 2007 | 37 | 2007 |
| FaulTM: Fault-tolerance using hardware transactional memory G Yalcin, O Unsal, I Hur, A Cristal, M Valero | 36 | 2010 |
| Exploring optimizations on shared-memory platforms for parallel triangle counting algorithms AS Tom, N Sundaram, NK Ahmed, S Smith, S Eyerman, M Kodiyath, I Hur, ... 2017 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2017 | 34 | 2017 |
| Many-core graph workload analysis S Eyerman, W Heirman, K Du Bois, JB Fryman, I Hur SC18: International Conference for High Performance Computing, Networking …, 2018 | 30 | 2018 |
| The velox transactional memory stack Y Afek, U Drepper, P Felber, C Fetzer, V Gramoli, M Hohmuth, E Riviere, ... IEEE micro 30 (5), 76-87, 2010 | 29 | 2010 |
| Memory controller with programmable regression model for power control I Hur, C Lin US Patent 7,724,602, 2010 | 29 | 2010 |
| Probabilistic method for performing memory prefetching I Hur, C Lin US Patent 7,856,533, 2010 | 27 | 2010 |
| Feedback mechanisms for improving probabilistic memory prefetching I Hur, C Lin 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 27 | 2009 |
| PIUMA: programmable integrated unified memory architecture S Aananthakrishnan, NK Ahmed, V Cave, M Cintra, Y Demir, KD Bois, ... arXiv preprint arXiv:2010.06277, 2020 | 25 | 2020 |
| STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems G Kestor, R Gioiosa, T Harris, OS Unsal, A Cristal, I Hur, M Valero Parallel Architectures and Compilation Techniques (PACT), 2011 International …, 2011 | 24 | 2011 |
Gulay YalcinAbdullah Gul University (AGU)Verified email at agu.edu.tr
