Nagesh B Lakshminarayana
Nagesh B Lakshminarayana
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Many-thread aware prefetching mechanisms for GPGPU applications
J Lee, NB Lakshminarayana, H Kim, R Vuduc
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 213-224, 2010
Age based scheduling for asymmetric multiprocessors
NB Lakshminarayana, J Lee, H Kim
Proceedings of the conference on high performance computing networking …, 2009
Power modeling for GPU architectures using McPAT
J Lim, NB Lakshminarayana, H Kim, W Song, S Yalamanchili, W Sung
ACM Transactions on Design Automation of Electronic Systems (TODAES) 19 (3 …, 2014
Macsim: A cpu-gpu heterogeneous simulation framework user guide
H Kim, J Lee, NB Lakshminarayana, J Sim, J Lim, T Pho
Georgia Institute of Technology, 1-57, 2012
Effect of instruction fetch and memory scheduling on GPU performance
NB Lakshminarayana, H Kim
Workshop on Language, Compiler, and Architecture Support for GPGPU 88, 2010
Spare register aware prefetching for graph algorithms on GPUs
NB Lakshminarayana, H Kim
2014 IEEE 20th international symposium on high performance computer …, 2014
DRAM scheduling policy for GPGPU architectures based on a potential function
NB Lakshminarayana, J Lee, H Kim, J Shin
IEEE Computer Architecture Letters 11 (2), 33-36, 2011
Asymmetry aware scheduling algorithms for asymmetric multiprocessors
N Lakshminarayana, S Rao, H Kim
Proc. of the Fourth Annual Workshop on the Interaction between Operating …, 2008
Sd3: An efficient dynamic data-dependence profiling mechanism
M Kim, NB Lakshminarayana, H Kim, CK Luk
IEEE Transactions on Computers 62 (12), 2516-2530, 2012
Macsim: Simulator for heterogeneous architecture
H Kim, J Lee, N Lakshminarayana, J Lim, T Pho
Georgia Institute of Technology, 2012
Understanding performance, power and energy behavior in asymmetric multiprocessors
NB Lakshminarayana, H Kim
2008 IEEE International Conference on Computer Design, 471-477, 2008
Tutorial on ocelot and sst-macsim simulator
H Kim, S Yalamanchili, J Lee, N Lakshminarayana, A Kerr, A Rodrigues, ...
ser. ISCA, 2012
Efficient graph algorithm execution on data-parallel architectures.
NB Lakshminarayana
Georgia Institute of Technology, Atlanta, GA, USA, 2015
Block-precise processors: Low-power processors with reduced operand store accesses and result broadcasts
NB Lakshminarayana, H Kim
IEEE Transactions on Computers 64 (11), 3102-3114, 2015
A Ferreron, A Samajdar, A Gutierrez, A Shriraman, A Rodrigues, B Asgari, ...
Block-Precise Processors: Low-Power Processors with Reduced Operand Store Writes and Result Broadcasts
NB Lakshminarayana, H Kim
IISWC 2009 reviewers
D August, L Barnes, P Dubey, L Eeckhout, P Faraboschi, J Held, M Hind, ...
2012 Index IEEE Computer Architecture Letters Vol. 11
EK Ardestani, J Chang, H Chen, J Chen, S Chen, X Chen, JM Codina, ...
Energy 21, 24, 0
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